Thesis - Study of the impact of short-circuit conditions on the robustness of GaN power transistor for aeronautic and automotive applications

The IRT Saint Exupéry* accelerates science, technological research and transfer to the aeronautics and space industries for the development of reliable, robust, certifiable and sustainable innovative solutions.

At our sites in Toulouse, Bordeaux, Montpellier, Sophia Antipolis and Montreal, we offer an integrated collaborative environment composed of engineers, researchers, experts and PhD students from academia and industry for research projects and R&T services supported by technological platforms around 4 axes: advanced manufacturing technologies, greener technologies, smart technologies and methods & tools for the development of complex systems.

Our developed technologies meet the needs of industry, integrating the results of academic research.

* We are a private research foundation, supported by the French government, which funds projects in proportion to the industrial contribution and defines the regulatory framework of the foundation.

Context :

We offer a challenging PhD thesis in a dynamic and multidisciplinary environment. The thesis is supported in the frame of the GANRET (Gallium Nitride Reliability for Trasnsport) project. The aim of the project is to enable the insertion of GaN based power electronics into severe environmental constrains applications. GANRET gathers several partners across different fields from space (ADS, Safran Electronics & Defense, TAS) to aeronautic with (Safran Electronics & Defense, Safran Tech and AIRBUS), including automotive with Vitesco Technology.
The industrial needs are complemented by a rich ecosystem of academic laboratories of test and technology investigation expertise and facilities. In particular the project integrates the national best-in-class scientific offer represented by four public laboratories (AMPERE à Lyon, IES à Montpellier, LAAS in Toulouse, SATIE in Paris) and a private academic laboratory (ICAM in Toulouse).

Description :

Several manufacturers of power semi-conductors components (EPC, GaN Systems, Panasonic, Transphorm, TI, Infineon…) propose HEMTs (High Electron Mobility Transistor) transistors in gallium nitride (GaN, which is a wide bandgap semiconductor material) for voltages between 100V and 650V. Physical properties of this material are superior to silicon ones; this allows the design of transistors with lower losses and higher switching frequencies. Thanks to the low conduction and switching losses, the dimension of the components can be drastically reduced with respect to a silicon transistor with similar current and voltage ratings. In this case, power density is increased which induces specific packaging requirements for the thermal management.

GaN transistors are based on an AlGaN/GaN heterostructure. At the interface of this heterostructure a bi-dimensional gas (2DEG) is generated. This gas has a very high electron density and mobility. Unlike Si or SiC power transistors, GaN HEMT have a lateral structure, meaning that current flows from the drain to the source within the same chip’s surface: this implies that the three electrodes (gate, drain and source) are on the same (top) face. This specificity requires the deposition of several metallization layers to distribute the control (gate) and power (drain and source) electrodes.

For power applications, the active area of the GaN HEMTs is generally deposited on a silicon substrate (hetero-epitaxy), mainly for cost reasons. This aspect brings lot of defects (like dislocation and impurities) in the GaN and AlGaN layers generating trapping. These traps correspond to energy levels in the GaN or AlGaN gap. Knowing that, charges can be trapped and detrapped. Depending on the state of the charges, the behaviour of the device can be affected, both during static and dynamic operation.

GaN transistors are very good candidates for the automotive and aeronautical industries and could be adopted in the near future. However, their robustness and reliability have not yet been fully mastered, particularly in the short-circuit regime. In such accidental state, the transistor finds itself in a conduction state with the full voltage of the DC bus across its terminals. Such an event can occur following, for example, a control fault. The short-circuit current is limited only by the internal characteristics of the component. It can reach values more than 10 times greater than the nominal current. These results in very high power dissipation, which leads to a very fast rise in chip temperature and can cause a catastrophic failure in a few hundred nanoseconds or a few microseconds if no protection is applied.

The short-circuit robustness of GaN transistors depends a lot on the applied drain-source voltage, but also on the control gate-source voltage and the considered transistor technology. Overall, GaN transistors tested in short circuit remain extremely fragile when subjected to a drain-source voltage greater than about 50% of its breakdown voltage.

The tests are generally not repeatable, especially under high drain-source voltage. It happens that on a series of identical components tested under the same conditions, some transistors break after a few hundred of nanoseconds, while others show a failure after several milliseconds.

PhD objectives and tasks :

The thesis has a double objective: to better understand de failure mechanisms of GaN HEMTs under short-circuit regime; and to find new protection strategies to ensure that such accidental event doesn’t impact nor alter the characteristic of the component.

In particular, the PhD candidate will be in charge of:

• Bibliography on the experimental work and modelling of GaN transistor under short-circuit conditions
• Participate to the implementation of different test benches, able to investigate:

-   Impact of drain-source voltage and gate voltage on the device reliability
-   Impact of electrical preconditioning and trapping on the device reliability
-   Impact of repetitive non-destructive short circuits events on device performances, with the objective to investigate whether any degradation appears
-   Maximum number of short-circuit, in function of the dissipated energy, that a device can support before failure
-   If possible, study of the reliability of several components in parallel

• Propose different strategies to protect the device in link with the obtained results 

• MSc degree in a relevant area of electrical engineering, or applied physics
• Good knowledge of specificity and behaviour of power semiconductors components
• Good experimental measurement skills in power electronics
• Ability to work with experts from a broad range of scientific and technology backgrounds

Involved partners :

The PhD thesis will take place mainly at the SATIE laboratory, at the site of ENS Paris-Saclay, in Gif sur Yvette. The PhD candidate will strictly collaborate with IRT Saint-Exupery: several trips to Toulouse will be therefore necessary.

IRT Saint-Exupery is one of the eight Institutes of Technology in France aiming to enhance R&D synergy between academia and industry. It fosters innovation by gathering partners around common roadblocks and builds projects on private-public funding basis to tackle them. This is a unique environment where industrial practical needs are directly matched to the scientific body of knowledge available in academia and research laboratories. The IRT Saint Exupery in Toulouse, in particular target this strategic industrial competitive edge in the following key areas: Reliability, green technologies, power electronics.
SATIE SATIE is a research laboratory of applied science. It is a joint CNRS research unit with 200 people. Our partners are: CNRS, l'ENS Paris-Saclay, l'ENS Rennes, le CNAM Paris, Cergy Paris Université, l'Université de Paris-Saclay et l'Université Gustave Eiffel. The scientific fields of the research ranges from electrical engineering to applied physics, including physics of systems and bio-microsystems.